The basic CMOS 6T SRAM cell in an integrated circuit (IC) generally includes two n-type or n-channel (NMOS) pull-down or drive transistors and two p-type (PMOS) pull-up or load transistors in a cross-coupled inverter configuration. Two additional NMOS select or pass-gate transistors are added to make up a standard double-sided or differential six-transistor memory cell (a DS 6T SRAM cell, a 6T SRAM cell, or simply a 6T cell). A 5 transistor SRAM cell (5T) use a single pass-gate transistor, and a 7T cell comprises a 5T cell together with a “read buffer” coupled to the 5T cell which comprises a series connected read pass transistor and a read driver transistor.
There is a general need for a stable compact memory cells with high READ current (Iread) per area, that operates at low power (e.g. low Quiescent supply current (IDDQ), that are stable during a READ operation and can be reliably written into. However, these characteristics generally contradict one another. For example, low threshold voltage (Vt) and/or short gate lengths generally provide high Iread, but also result in high subthreshold leakage and poor cell stability. Longer channel lengths and/or higher Vt reduce subthreshold leakage and improve cell stability but degrade Iread, especially at low VDD. Similarly, changes in the transistors (such as width, length, or threshold voltage) that improve the stability during a READ generally degrade the robustness of the WRITE.
An 8T SRAM cell comprising a 6T core SRAM cell and a read buffer with separate read wordline (WL) and separate read bitline (BL) has been proposed to separate READ functionality from WRITE functionality. However, this separation of READ functionality and WRITE functionality of the conventional 8T is not effective in conventional SRAM architectures where words are interleaved in a row. Cells that are in a selected row but not a selected column (half selected cells) are subject to upset in a WRITE cycle. This upset of half selected cells can be remedied by READ and WRITE back, but additional peripheral circuitry is needed to sense the read bit lines (RBL) and drive the write bit lines (WBL) for half selected cells in a WRITE cycle.